On the balance property of Patricia tries: external path length viewpoint
Theoretical Computer Science
Memory segmentation to exploit sleep mode operation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Memory exploration for low power, embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Towards a theory of cache-efficient algorithms
SODA '00 Proceedings of the eleventh annual ACM-SIAM symposium on Discrete algorithms
Architecture-level power estimation and design experiments
ACM Transactions on Design Automation of Electronic Systems (TODAES)
JouleTrack: a web based tool for software energy profiling
Proceedings of the 38th annual Design Automation Conference
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Memory controller policies for DRAM power management
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
System-level interconnect architecture exploration for custom memory organizations
Proceedings of the 14th international symposium on Systems synthesis
Layout-driven memory synthesis for embedded systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Random-Access Data Storage Components in Customized Architectures
IEEE Design & Test
Data Memory Organization and Optimizations in Application-Specific Systems
IEEE Design & Test
Influence of Array Allocation Mechanisms on Memory System Energy
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
I/O complexity: The red-blue pebble game
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
Distributed Prefetch-buffer/Cache Design for High Performance Memory Systems
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Cache conscious Walsh-Hadamard transform
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
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Energy dissipation is a critical concern for battery-powered embedded systems. Memory energy contributes significantly to overall energy in data intensive applications. Low power memory systems are being designed that support multiple power states of memory banks. In low power states, energy dissipation is reduced but time to access memory is increased.We abstract an energy model for the memory system and exploit it to develop algorithmic techniques for memory energy reduction. This is achieved by exploring the structure and data access pattern of a given algorithm to devise memory power management schedules. We illustrate our approach through two well-known embedded benchmarks - Matrix Multiplication and Fast Fourier Transform. The optimality of our schemes is discussed using information theoretic lower bounds on memory energy. Simulations demonstrate that significant energy reduction can be achieved by using our approach over state-of-the-art implementations.