ESTIMA: an architectural-level power estimator for multi-ported pipelined register files

Authors:
Kavel M. Büyüksahin;Priyadarsan Patra;Farid N. Najm
Affiliations:
Intel Corp, Hillsboro, OR;Intel Corp, Hillsboro, OR;University of Toronto, Toronto, ON, Canada
Venue:
Proceedings of the 2003 international symposium on Low power electronics and design
Year:
2003

Citing 4
Cited 1

Analytical energy dissipation models for low-power caches

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
The SimpleScalar tool set, version 2.0

ACM SIGARCH Computer Architecture News
The energy complexity of register files

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Wattch: a framework for architectural-level power analysis and optimizations

Proceedings of the 27th annual international symposium on Computer architecture

EMPIRE: Empirical power/area/timing models for register files

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

We introduce an architectural-level power, area, and latency estimator for multi-ported, pipelined register files. Strengths of the proposed approach include the handling of pipelined operation and clock power, the simulation-based device size estimation, and the ability to handle user-specified timing constraints. The model proposed can be used as a stand-alone estimation and design exploration tool for register files and register-file type structures, or it can be incorporated into a high-level performance simulator to add power estimation capabilities.