Selective eager execution on the PolyPath architecture
Proceedings of the 25th annual international symposium on Computer architecture
The energy complexity of register files
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Decoupling local variable accesses in a wide-issue superscalar processor
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Software-Directed Register Deallocation for Simultaneous Multithreaded Processors
IEEE Transactions on Parallel and Distributed Systems
Inherently Lower-Power High-Performance Superscalar Architectures
IEEE Transactions on Computers
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Banked multiported register files for high-frequency superscalar microprocessors
Proceedings of the 30th annual international symposium on Computer architecture
A Speculative Control Scheme for an Energy-Efficient Banked Register File
IEEE Transactions on Computers
Register port complexity reduction in wide-issue processors with selective instruction execution
Microprocessors & Microsystems
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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The register file is a key datapath component of a superscalar microprocessor. Its access time is critical since it can impact cycle time. Its size can easily become a problem: superscalar microprocessors have a large number of ports (typically 10 for a three-scalar machine) and the size is quadratic in the number of ports. The "3D Register File " uses the area inherently consumed by the metal wires used for the word and bit lines for each cell to hide N sets of registers. Each set is logically a plane in the third dimension. The ability to access multiple planes can be used for register windows or for extra register sets for real time tasks or microtask switching. The data array of a 3D eight-window 10 ported register file is six times smaller than a flat register file. Access time is sped up by shortening bus lines and by sharing a large buffer between bit cells. The 3D register file has been implemented on two high performance superscalar processors and early silicon confirms our simulations.