Performance and power evaluation of an intelligently adaptive data cache

Authors:
Domingo Benítez;Juan Carlos Moure;Dolores Isabel Rexachs;Emilio Luque
Affiliations:
DIS Department & IUSIANI, University of Las Palmas G.C., Las Palmas, Spain;Computer Architecture and Operating Systems (CAOS) Department, Universidad Autónoma de Barcelona, Barcelona, Spain;Computer Architecture and Operating Systems (CAOS) Department, Universidad Autónoma de Barcelona, Barcelona, Spain;Computer Architecture and Operating Systems (CAOS) Department, Universidad Autónoma de Barcelona, Barcelona, Spain
Venue:
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
Year:
2005

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Abstract

We describe the analysis of an on-line pattern-recognition algorithm to dynamically control the configuration of the L1 data cache of a high-performance processor. The microarchitecture achieves higher performance and energy saving due to the accommodation of operating frequency, capacity, set-associativity, line size, hit latency, energy per access, and chip area to program workload and ILP. We show that for the operating frequency 4.5 GHz, the execution time is always reduced with an average measure of 12.1% when compared to a non-adaptive high-performance processor. Additionally, the energy saving is 2.7% on average, and t1he product time-energy is reduced on average by 14.9%. We also consider a profile-based reconfiguration of data cache, which allows picking different cache configurations but only one can be chosen for each program. Experimental results indicate that this approach yields a high percentage of the performance improvement and energy saving achieved by the on-line algorithm.