On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
OpenMP: An Industry-Standard API for Shared-Memory Programming
IEEE Computational Science & Engineering
Power Efficient Processor Architecture and The Cell Processor
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
An FPGA Parallel Sorting Architecture for the Burrows Wheeler Transform
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
The potential of the cell processor for scientific computing
Proceedings of the 3rd conference on Computing frontiers
Scan primitives for GPU computing
Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
BSGP: bulk-synchronous GPU programming
ACM SIGGRAPH 2008 papers
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
An Architecture for Inline Anomaly Detection
EC2ND '08 Proceedings of the 2008 European Conference on Computer Network Defense
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Accelerating Compute-Intensive Applications with GPUs and FPGAs
SASP '08 Proceedings of the 2008 Symposium on Application Specific Processors
Designing efficient sorting algorithms for manycore GPUs
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
Sorting on architecturally diverse computer systems
Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications
State-of-the-art in heterogeneous computing
Scientific Programming
Intrinsic evolution of sorting networks: a novel complete hardware implementation for FPGAs
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
ANCS '13 Proceedings of the ninth ACM/IEEE symposium on Architectures for networking and communications systems
Real-time motion detection based on SW/HW-codesign for walking rescue robots
Journal of Real-Time Image Processing
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Currently there are several interesting alternatives for low-cost high-performance computing. We report here our experiences with an N-gram extraction and sorting problem, originated in the design of a real-time network intrusion detection system. We have considered FPGAs, multi-core CPUs in symmetric multi-CPU machines and GPUs and have created implementations for each of these platforms. After carefully comparing the advantages and disadvantages of each we have decided to go forward with the implementation written for multicore CPUs. Arguments for and against each platform are presented - corresponding to our hands-on experience - that we intend to be useful in helping with the selection of the hardware acceleration solutions for new projects.