Intrinsic evolution of sorting networks: a novel complete hardware implementation for FPGAs

Authors:
Jan Kořenek;Lukáš Sekanina
Affiliations:
Faculty of Information Technology, Brno University of Technology, Brno, Czech Republic;Faculty of Information Technology, Brno University of Technology, Brno, Czech Republic
Venue:
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
Year:
2005

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Abstract

A specialized architecture was developed and evaluated to evolve relatively large sorting networks in an ordinary FPGA. Genetic unit and fitness function are also implemented on the same FPGA. We evolved sorting networks up to N = 28. The evolution of the largest sorting networks requires 10 hours in FPGA running at 100 MHz. The experiments were performed using COMBO6 card.