Complexity-effective superscalar processors
Proceedings of the 24th annual international symposium on Computer architecture
Power and energy reduction via pipeline balancing
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Select-free instruction scheduling logic
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
POWER4 system microarchitecture
IBM Journal of Research and Development
Low complexity out-of-order issue logic using static circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A fundamental property of superscalar architectures is the execution of multiple instructions per cycle. To accomplish this, the issue logic selects and prioritizes the instructions whose operands will be ready in the next cycle, using wakeup, select and queue update logic. By incorporating the issue logic in one pipeline stage, dependent instructions can be issued in consecutive cycles. However, the many serial operations required makes this problematic from a circuit delay perspective. In this paper, we propose an issue queue design that divides the ready signals into groups, sorts the groups in parallel and provides four oldest ready instructions for issue, with single-cycle operation. Static CMOS select and update logic reduces power and low fan-out in many stages improves circuit speed. The complete issue logic requires 30 inversions, allowing simulated circuit operation at over 3 GHz in a foundry 45nm SOI fabrication process.