Low complexity out-of-order issue logic using static circuits

Authors:
Siddhesh S. Mhambrey;Satendra K. Maurya;Lawrence T. Clark
Affiliations:
School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ;School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ;School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2013

Citing 9
Cited 0

Complexity-effective superscalar processors

Proceedings of the 24th annual international symposium on Computer architecture
Power and energy reduction via pipeline balancing

ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Select-free instruction scheduling logic

Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
A high-speed dynamic instruction scheduling scheme for superscalar processors

Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
The Alpha 21264 Microprocessor Architecture

ICCD '98 Proceedings of the International Conference on Computer Design
Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors

IBM Journal of Research and Development - Electrochemical technology in microelectronics
Computer Architecture, Fourth Edition: A Quantitative Approach

Computer Architecture, Fourth Edition: A Quantitative Approach
Matrix scheduler reloaded

Proceedings of the 34th annual international symposium on Computer architecture
Out-of-order issue logic using sorting networks

Proceedings of the 20th symposium on Great lakes symposium on VLSI

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper a single-cycle issue queue circuit architecture that simplifies the wakeup and selection logic is proposed. The micro-architecture and fully static CMOS circuits are presented for a 32-entry queue that issues four instructions per cycle. The instruction-ready signals are divided into groups and processed in parallel to issue the four oldest ready instructions. The complete issue queue and prioritization logic requires 20 inversions, allowing simulated circuit operation at over 4 GHz in a foundry 45 nm SOI fabrication process.