Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Fat-trees: universal networks for hardware-efficient supercomputing
IEEE Transactions on Computers
Three dimensional circuit layouts
SIAM Journal on Computing
Equivalence of multistage interconnection networks
Information Processing Letters
Sorting in c log n parallel steps
Combinatorica
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Introduction to parallel algorithms and architectures: array, trees, hypercubes
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
A complexity theory for VLSI
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
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This paper proposes a new metric that aims to express the cost of manufacturing large-scale, communication-intensive digital systems. These systems are modeled by networks with internal and external edges, where the latter are input/output edges connecting the system with the external world. A k–parceling of such a network is a partition of the network into components each having at most k non-internal edges. (Such a partition is of interest when the number of the external edges is much larger than k.) The k–parceling number of a network is the minimal number of components in a k–parceling. We argue that the parceling number of a large-scale, communication-intensive network expresses the cost of such a system better than the contemporary prevalent metrics and therefore it can guide the designers of such systems better than these metrics. The paper studies the parceling of two important networks, the Butterfly and the Batcher Bitonic sorting network. It establishes explicit (rather than asymptotic) lower and upper bounds on the parceling number of both networks.