Reduced-complexity mimo detector with close-to ml error rate performance
Proceedings of the 17th ACM Great Lakes symposium on VLSI
An architecture for energy efficient sphere decoding
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Relaxed K-best MIMO signal detector design and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm
Proceedings of the 19th ACM Great Lakes symposium on VLSI
High-throughput low-complexity MIMO detector based on K-best algorithm
Proceedings of the 19th ACM Great Lakes symposium on VLSI
IEEE Journal on Selected Areas in Communications - Special issue on realizing GBPS wireless personal area networks
A low-area flexible MIMO detector for WiFi/WiMAX standards
Proceedings of the Conference on Design, Automation and Test in Europe
VLSI implementation of a fixed-complexity soft-output MIMO detector for high-speed wireless
EURASIP Journal on Wireless Communications and Networking
A High Throughput Configurable SDR Detector for Multi-user MIMO Wireless Systems
Journal of Signal Processing Systems
Application exploration for 3-d integrated circuits: TCAM, FIFO, and FFT case studies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implementation of a High-Speed MIMO Soft-Output Symbol Detector for Software Defined Radio
Journal of Signal Processing Systems
Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors
Journal of Signal Processing Systems
Algorithm and implementation of the K-best sphere decoding for MIMO detection
IEEE Journal on Selected Areas in Communications
Soft-output sphere decoding: algorithms and VLSI implementation
IEEE Journal on Selected Areas in Communications
IEEE Journal on Selected Areas in Communications
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K-best sphere decoding is one of the most popular MIMO (Multi-Input Multi-Output) detection algorithms because of its low complexity and close to Maximum Likelihood (ML) Bit Error Rate (BER) performance. Unfortunately, conventional multi-stage sphere decoders suffer from the inability to adapt to varying antenna configurations, requiring implementation redesign for each specific array structure. In this paper, we propose a reconfigurable in-place architecture that is scalable to an arbitrary number of antennas at run-time, while reducing area significantly compared with other sphere decoders. To improve the throughput of the in-place architecture without any degradation in BER performance, we propose partial-sort-bypass and symbol interleaving techniques, and also exploit multi-core design. Implementation results for a 16-QAM MIMO decoder in a 130 nm CMOS technology show a 41% reduction in area compared to the smallest sphere decoder while maintaining antenna reconfigurability, and better throughput. When implemented for the 802.11n standard, our architecture results in 42% reduction in area compared to the multi-stage architecture.