Low-power silicon architecture for wireless communications: embedded tutorial
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Closing the power gap between ASIC and custom: an ASIC perspective
Proceedings of the 42nd annual Design Automation Conference
Advanced receiver algorithms for MIMO wireless communications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Algorithm and implementation of the K-best sphere decoding for MIMO detection
IEEE Journal on Selected Areas in Communications
Array like runtime reconfigurable MIMO detectors for 802.11n WLAN: a design case study
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
High-throughput low-complexity MIMO detector based on K-best algorithm
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Algorithm and hardware complexity reduction techniques for k-best sphere decoders
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Small-area and low-energy K-best MIMO detector using relaxed tree expansion and early forwarding
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
A low-area flexible MIMO detector for WiFi/WiMAX standards
Proceedings of the Conference on Design, Automation and Test in Europe
Area-Efficient Antenna-Scalable MIMO Detector for K-best Sphere Decoding
Journal of Signal Processing Systems
| Hi-index | 0.00 |
Sphere Decoding has become a popular implementation of MIMO decoding due to its improved performance at lower hardware complexity. Present ASIC implementations fail to consider sources of pipelinability and parallelism in the algorithm to achieve reduced power. In this work, we provide a proposal and initial results for an improved architecture which aims to increase overall energy efficiency (b/s/mW) of the decoder. This improvement is based on a novel implementation which combines the use of a deeply pipelined data-path and "multi symbol vector" based approach to exploit the pipeline. Implementation in 0.18μ 1.8V CMOS technology provides an operational frequency of 128/230(retimed)MHz at 409 mW(DFF memory)/ 360 mW(realistic memory) and 3.44 sq.mm (DFF memory).