Advanced receiver algorithms for MIMO wireless communications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An architecture for energy efficient sphere decoding
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Relaxed K-best MIMO signal detector design and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm
Proceedings of the 19th ACM Great Lakes symposium on VLSI
High-throughput low-complexity MIMO detector based on K-best algorithm
Proceedings of the 19th ACM Great Lakes symposium on VLSI
IEEE Journal on Selected Areas in Communications - Special issue on realizing GBPS wireless personal area networks
A High Throughput Configurable SDR Detector for Multi-user MIMO Wireless Systems
Journal of Signal Processing Systems
Algorithm and implementation of the K-best sphere decoding for MIMO detection
IEEE Journal on Selected Areas in Communications
IEEE Journal on Selected Areas in Communications
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MIMO (Multi-Input Multi-Output) technology is garnering more interest in new wireless communication standards. In this work, we introduce three techniques to reduce the power consumption of MIMO detectors and increase their data rate. We decrease the complexity of the K-best sphere decoder effectively by using the MMSE-SQRD channel processing technique. This technique results in a smaller K which results in a great reduction in power consumption compared to the K-best detectors using ZF-SQRD with the same BER/throughput performance. We also propose a child reduction technique that reduces the number of multiplications and additions which results in 8% power reduction. Also, we utilized the odd-even merge algorithm for the merge unit which is on the critical path of the circuit, to achieve the best power/throughput tradeoff. We implemented a 4*4 16QAM detector in a commercial 0.18µm CMOS process; synthesis results show that the detector works at the maximum data rate of 768Mbps with the area of 91KGates.