On a Class of Multistage Interconnection Networks
IEEE Transactions on Computers
The Performance of Multistage Interconnection Networks for Multiprocessors
IEEE Transactions on Computers
A Survey of Interconnection Networks
Computer
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
Burst switching--An introduction
IEEE Communications Magazine
Performance Analysis of a Packet Switch Based on Single-Buffered Banyan Network
IEEE Journal on Selected Areas in Communications
Gauss: a simple high performance switch architecture for ATM
SIGCOMM '90 Proceedings of the ACM symposium on Communications architectures & protocols
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The basic criteria and present trends in the design of asynchronous transfer mode switching architectures for broadband applications are outlined. The main differences between various structures proposed in the literature are identified, and their performances in terms of throughput and delay are discussed. In particular, a comparison between single and multistage architectures is presented. The paper concludes with a brief description of the main non-blocking ATM switching structures.