Lattice basis reduction: improved practical algorithms and solving subset sum problems
Mathematical Programming: Series A and B
Fundamentals of wireless communication
Fundamentals of wireless communication
Relaxed K-best MIMO signal detector design and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
Probabilistic spherical detection and VLSI implementation for multiple-antenna systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers
On the sphere-decoding algorithm I. Expected complexity
IEEE Transactions on Signal Processing - Part I
Algorithm and implementation of the K-best sphere decoding for MIMO detection
IEEE Journal on Selected Areas in Communications
Small-area and low-energy K-best MIMO detector using relaxed tree expansion and early forwarding
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Small-area and low-energy K-best MIMO detector using relaxed tree expansion and early forwarding
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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The multiple-input-multiple-output (MIMO) technique is being actively adopted in recent wireless communication standards to enhance data rate. Though channel capacity is increased by adopting multiple spatial streams, the computational complexity needed to eliminate the interference hinders the implementation of a practical system. In this paper, we propose a modified Dijkstra's algorithm and a precalculation technique to improve the throughput by allowing overlapped processing. For the maximum-likelihood (ML) detection, in addition, we propose a simple approximation of L2-norm calculation to reduce the computational complexity without degrading the error performance noticeably. A MIMO symbol detector based on the proposed algorithm is implemented in a 0.18-µm CMOS process, targeting 4 × 4 16-QAM. It occupies about 0.5 mm2 with 25.1 K equivalent gates and shows a throughput of over 300 Mb/s.