Sorting on a mesh-connected parallel computer
Communications of the ACM
Bitonic Sort on a Mesh-Connected Parallel Computer
IEEE Transactions on Computers
Optimal Sorting Algorithms for Parallel Computers
IEEE Transactions on Computers
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
IEEE Transactions on Computers
A Model of SIMD Machines and a Comparison of Various Interconnection Networks
IEEE Transactions on Computers
AFIPS '62 (Fall) Proceedings of the December 4-6, 1962, fall joint computer conference
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
IEEE Transactions on Computers
An ASIC design and formal analysis of a novel pipelined and parallel sorting accelerator
Integration, the VLSI Journal
The VLSI Complexity of Sorting
IEEE Transactions on Computers
Hi-index | 14.99 |
An algorithm is presented to merge two subfiles of size n/2 each, stored in the left and the right halves of a linearly connected processor array, in 3n/2 route steps and log n compare-exchange steps. This algorithm is extended to merge two horizontally adjacent subfiles of size m 脳 n/2 each, stored in an m 脳 n mesh-connected processor array in row-major order, in m + 2n route steps and log mn compare-exchange steps. These algorithms are faster than their counterparts proposed so far.