A "zero-time" VLSI sorter

Authors:
G. Miranker;L. Tang;C. K. Wong
Affiliations:
Valid Logic Systems, Inc., Sunnyvale, California;Switchco Inc., Teaneck, New Jersey;IBM Research Division, Yorktown Heights, New York
Venue:
IBM Journal of Research and Development
Year:
1983

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Abstract

A hardware sorter suitable for VLSI implementation is proposed. It operates in a parallel and pipelined fashion, with the actual sorting time absorbed by the input/output time. A detailed VLSI implementation is described which has a very favorable device count compared to existing static RAM.