Journal of the ACM (JACM)
Journal of the ACM (JACM)
An Adaptation of the Fast Fourier Transform for Parallel Processing
Journal of the ACM (JACM)
Sorting Using Networks of Queues and Stacks
Journal of the ACM (JACM)
ACM Computing Surveys (CSUR)
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
AN ANALYSIS OF SORTING NETWORKS
AN ANALYSIS OF SORTING NETWORKS
A lower bound for sorting networks that use the divide-sort-merge strategy
A lower bound for sorting networks that use the divide-sort-merge strategy
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
System Design of a Cellular APL Computer
IEEE Transactions on Computers
Sequential Permutation Networks
IEEE Transactions on Computers
Cellular Interconnection Arrays
IEEE Transactions on Computers
The Anticipatory Control of a Cyclically Permutable Memory
IEEE Transactions on Computers
Cellular Logic-in-Memory Arrays
IEEE Transactions on Computers
IEEE Transactions on Computers
Universal connecting networks and the synthesis of canonical sequential circuits
SWAT '68 Proceedings of the 9th Annual Symposium on Switching and Automata Theory (swat 1968)
Topological constraints on interconnection-limited logic
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
Sorting networks and their applications
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
A study of the data commutation problems in a self-repairable multiprocessor
AFIPS '68 (Spring) Proceedings of the April 30--May 2, 1968, spring joint computer conference
Programmable indexing networks
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
The architecture of a large associative processor
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
A systematic approach to the design of digital bussing structures
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
Evaluation of On-Chip Static Interconnection Networks
IEEE Transactions on Computers
Programming cellular permutation networks through decomposition of symmetric groups
IEEE Transactions on Computers
ACM Transactions on Programming Languages and Systems (TOPLAS)
A Cluster Structure as an Interconnection Network for Large Multimicrocomputer Systems
IEEE Transactions on Computers
Communication Structures for Large Networks of Microcomputers
IEEE Transactions on Computers
Parallel Solution of Ordinary Differential Equations
IEEE Transactions on Computers
Interconnection Networks from Three State Cells
IEEE Transactions on Computers
Fault Diagnosis in a Boolean n Cube Array of Microprocessors
IEEE Transactions on Computers
On a Class of Multistage Interconnection Networks
IEEE Transactions on Computers
Pin Limitations and Partitioning of VLSI Interconnection Networks
IEEE Transactions on Computers
A Classification of Cube-Connected Networks with a Simple Control Scheme
IEEE Transactions on Computers
| Hi-index | 0.03 |
As the level of complexity of digital systems increases, the problem of interconnecting subunits is receiving increasing attention. We are reaching the point where processing speed cannot be further improved through the use of faster componentry. Further speed-up of systems will most likely result from changes in the organization and structure of hardware, rather than by raw circuit improvements. Another factor increasing the complexity of systems is the arrival of cheap, powerful LSI microcomputers which allow system construction involving a plurality of processors connected together to perform a specific task. Restructurable system concepts are also very promising, but require extensive amounts of interconnective capability. Thus, bus structures are attracting considerable attention. This paper focuses on a small segment of the general bus structure problem; namely, interconnection (permutation, sorting, etc.) networks.