Communications of the ACM
An iteratively structured digital computer
An iteratively structured digital computer
Distributed logic memory computer for process control
Distributed logic memory computer for process control
A programming language
Cellular Interconnection Arrays
IEEE Transactions on Computers
A Multiaccess Associative Memory
IEEE Transactions on Computers
Path Finding with Associative Memory
IEEE Transactions on Computers
Determination of Priority in Associative Memories
IEEE Transactions on Computers
A cryotron catalog memory system
AIEE-IRE '56 (Eastern) Papers and discussions presented at the December 10-12, 1956, eastern joint computer conference: New developments in computers
A universal computer capable of executing an arbitrary number of sub-programs simultaneously
IRE-AIEE-ACM '59 (Eastern) Papers presented at the December 1-3, 1959, eastern joint IRE-AIEE-ACM computer conference
Intercommunicating cells, basis for a distributed logic computer
AFIPS '62 (Fall) Proceedings of the December 4-6, 1962, fall joint computer conference
Some applications for content-addressable memories
AFIPS '63 (Fall) Proceedings of the November 12-14, 1963, fall joint computer conference
An associative parallel processor with application to picture processing
AFIPS '65 (Fall, part I) Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
The associative memory structure
AFIPS '65 (Fall, part I) Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
ASP: a new concept in language and machine organization
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
The architecture of a context addressed segment-sequential storage
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
A study of fault tolerance techniques for associative processors
AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
Interconnection networks: a survey and assessment
AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
On a varistructured array of microprocessors
IEEE Transactions on Computers - Special issue on parallel processors and processing
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This paper will describe features of architectural significance to the segmentability of a processor; it is not intended to be a detailed description of a processor for Information Storage and Retrieval. We regret that the incorporation of some features cannot be defended here because of the length of this paper. They are presented in a report. We first state the types of problems to be processed. This will lead to the overall organization of the processor. In Information Storage and Retrieval, a processor should have the capability to store data which is formatted as ordered sets or unordered sets, and to retrieve all such sets having a specified subset. An unordered set search for a given subset S retrieves all sets containing S. An ordered set search for a given ordered subset S retrieves all ordered sets containing S. A string search for a given string S retrieves all ordered sets (strings) having a substring S. For example, if S = (s1, s2, s3) and S1 = (s1, a, s2, s3), S2 = (a, b, s1), s2, s3, c, d), S3 = (s2, s1, s3) and S4 = (s1, a, b, s2). Then an unordered set search for S would retrieve S1, S2, S3, an ordered set search for S would retrieve S1 and S2, and a string search for S would retrieve S2.