A virtual memory for microprocessors
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
A hierarchical, restructurable multi-microprocessor architecture
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
A varistructured fail-soft cellular computer
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Theory of Self-Reproducing Automata
Theory of Self-Reproducing Automata
On Generating Multipliers for a Cellular Fast Fourier Transform Processor
IEEE Transactions on Computers
ILLIAC IV Software and Application Programming
IEEE Transactions on Computers
A universal computer capable of executing an arbitrary number of sub-programs simultaneously
IRE-AIEE-ACM '59 (Eastern) Papers presented at the December 1-3, 1959, eastern joint IRE-AIEE-ACM computer conference
D825 - a multiple-computer system for command & control
AFIPS '62 (Fall) Proceedings of the December 4-6, 1962, fall joint computer conference
The architecture of a large associative processor
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
Distributed intelligence for user-oriented computing
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
ACM SIGARCH Computer Architecture News
An organization for optical linkages between integrated circuits
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
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The varistructure architecture gives the user the opportunity to specify the height and width of his primary memory "at run time." This architecture, first proposed in 1973, has now been simplified to make it schedulable, extended to allow SIMD vector-vector operations, and further extended to provide variable structure within a task. Memory is efficiently utilized in that memory bandwidth can be increased for array processing, yet memory space is not wasted during string processing. The fetch-execute cycle operation is analyzed herein, and some tentative results regarding input-output and data communication between processing entities are reported. On the basis of the simplicity of the fetch-execute cycle, there is hope that this architecture may well be the best way to build minicomputers and large computers using a cellular array of microprocessors.