Computer Interconnection Structures: Taxonomy, Characteristics, and Examples
ACM Computing Surveys (CSUR)
Introduction to VLSI Systems
A preliminary architecture for a basic data-flow processor
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
Asynchronous and clocked control structures for VLSI based interconnection networks
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Design issues in the development of a modular multiprocessor communications network
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
A large scale, homogeneous, fully distributed parallel machine, I
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
VLSI Performance Comparison of Banyan and Crossbar Communications Networks
IEEE Transactions on Computers
Anomalous Behavior of Synchronizer and Arbiter Circuits
IEEE Transactions on Computers
Theoretical and Experimental Behavior of Synchronizers Operating in the Metastable Region
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
Cm*: a modular, multi-microprocessor
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
Interconnection networks: a survey and assessment
AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
An overview of the Texas reconfigurable array computer
AFIPS '80 Proceedings of the May 19-22, 1980, national computer conference
Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
IEEE Transactions on Computers
On the permutation capability of multistage interconnection networks
IEEE Transactions on Computers
Traffic-Specific Interconnection Networks for Multicomputers
IEEE Transactions on Computers
Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Asynchronous and Clocked Control Structures for VSLI Based Interconnection Networks
IEEE Transactions on Computers
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Multiple processor interconnection networks can be characterized as having N' inputs and N' outputs, each being B' bits wide. A major implementation constraint of large networks in the VLSI environment is the number of pins available on a chip, Np. Construction of large networks requires partitioning of the N' * N' * B' network into a collection of N * N switch modules with each input and output port being B (B = B') bits wide. If each module corresponds to a single chip, then a large network can be implemented by interconnecting the chips in a particular manner. This correspondence presents a methodology for selecting the optimum values of N and B given values of N', B', Np, and the number of control lines per port. Models for both banyan and crossbar networks are developed and arrangements yielding minimum: 1) number of chips, 2) average delay through the network, and 3) product of number of chips and delay, are presented.