Introduction to VLSI Systems
A preliminary architecture for a basic data-flow processor
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
Asynchronous and clocked control structures for VLSI based interconnection networks
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Signal delay in RC tree networks
DAC '81 Proceedings of the 18th Design Automation Conference
Design issues in the development of a modular multiprocessor communications network
ISCA '79 Proceedings of the 6th annual symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
A large scale, homogeneous, fully distributed parallel machine, I
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
VLSI Performance Comparison of Banyan and Crossbar Communications Networks
IEEE Transactions on Computers
The Indirect Binary n-Cube Microprocessor Array
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
Pin Limitations and Partitioning of VLSI Interconnection Networks
IEEE Transactions on Computers
Access and Alignment of Data in an Array Processor
IEEE Transactions on Computers
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Cm*: a modular, multi-microprocessor
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
Modular crossbar switch for large-scale multiprocessor systems: structure and implementation
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
An overview of the Texas reconfigurable array computer
AFIPS '80 Proceedings of the May 19-22, 1980, national computer conference
A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Theory of Generalized Branch and Combine Clock Networks
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Efficient clock distribution scheme for VLSI RNS-Enabled controllers
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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A central issue in the design of multiprocessor systems is the interconnection network which provides communication paths between the processors. For large systems, high bandwidth interconnection networks will require numerous "network chips" with each chip implementing some subnetwork of the original larger network. Modularity and growth are important properties for such networks since multiprocessor systems may vary in size. This paper is concerned with the question of timing control of such networks. Two approaches, asynchronous and clocked, are used in the design of a basic network switching module. The modules and the approaches are then modeled and equations for network time delay are developed. These equations form the basis for a comparison between the two approaches. The importance of clock distribution strategies and clock skew is quantified, and a network clock distribution scheme which guarantees equal length clock paths is presented.