Residue number system arithmetic: modern applications in digital signal processing
Residue number system arithmetic: modern applications in digital signal processing
Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Timing constraints for high-speed counterflow-clocked pipelining
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic
Journal of VLSI Signal Processing Systems
Asynchronous and Clocked Control Structures for VSLI Based Interconnection Networks
IEEE Transactions on Computers
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Synchronization of VLSI systems is growing in complexity because of the increase in die size and integration levels, along with stronger requirements for integrated circuit speed and reliability. The size increase leads to delays and synchronization losses in clock distribution. Additionally, the large amount of synchronous hardware in integrated circuits requires large current spikes to be drawn from the power supply when the clock changes state. This paper presents a new approach for clock distribution in RNS-based systems, where channel independence removes clock timing restrictions. This approach generates several clock signals with non-overlapping edges from a global clock. This technique shows a significant decrease in instantaneous current requirements and a homogeneous time distribution of current supply to the chip, while keeping extra hardware to a minimum and introducing an affordable power cost, as shown through simulation.