A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine

VHDL & Verilog compared & contrasted—plus modeled example written in VHDL, Verilog and C

DAC '96 Proceedings of the 33rd annual Design Automation Conference

A formal description of VHDL-AMS analogue systems

Proceedings of the conference on Design, automation and test in Europe

Formal Semantics for VHDL

Formal Semantics for VHDL

A semantic model for VHDL-AMS

Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification

An approach to Verilog-VHDL interoperability for synchronous designs

Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification

The Semantic Challenge of Verilog HDL

LICS '95 Proceedings of the 10th Annual IEEE Symposium on Logic in Computer Science

3.3: Verilog Nonblocking Assignments Demystified

IVC-VIUF '98 Proceedings of the International Verilog HDL Conference and VHDL International Users Forum