A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine
DATE '99 Proceedings of the conference on Design, automation and test in Europe
IEEE Standard Description Language Based on the VERILOG Hardware Description Language, 1364-1995
IEEE Standard Description Language Based on the VERILOG Hardware Description Language, 1364-1995
Symbolic Model Checking
Symbolic Reachability Analysis Based on SAT-Solvers
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic Verification of Finite-state Concurrent Systems
Proceedings of the 15th International Conference on Application and Theory of Petri Nets
The Verus Tool: A Quantitative Approach to the Formal Verification of Real-Time Systems
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Compiling Verilog into timed finite state machines
IVC '95 Proceedings of the 4th IEEE International Verilog HDL Conference
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Since the advent of model checking it is becoming more common for languages to be given a semantics in terms of transition systems. Such semantics allow to model check properties of programs but are usually difficult to formally reason about, and thus do not provide a sufficiently abstract description of the semantics of a language. We present a set of transition system combinators that allow abstract and compositional means of expressing language semantics. These combinators are then used to express the semantics of a subset of the Verilog hardware description language. This approach allows reasoning about the language using both model checking and standard theorem proving techniques.