Crafting a compiler
HSIS: a BDD-based environment for formal verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Symbolic Model Checking
The VERILOG Hardware Description Language
The VERILOG Hardware Description Language
Verilog HDL Modeling Styles for Formal Verification
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Fast discrete function evaluation using decision diagrams
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An Automatic Controller Extractor for HDL Descriptions at the RTL
IEEE Design & Test
The Semantics of Verilog Using Transition System Combinators
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Automatic circuit extractor for HDL description using program slicing
Journal of Computer Science and Technology - Special issue on computer graphics and computer-aided design
Generating finite state machines from SystemC
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
| Hi-index | 0.00 |
The lack of formal semantics for HDLs has made it hard to make a formal bridge between simulation tools based on HDLs and synthesis/verification tools based on finite state machines. We address the problem of finding a larger subset of Verilog HDL (which includes timing constructs) and a systematic way of extracting FSMs from programs built using the subset. Using timed FSMs as the target language for HDL compilation gives us two potential advantages. First, FSMs can be used to model systems that do not have hardware implementation. Second, FSMs can be used to model systems that are implementable but not automatically synthesizable.