System Design with SystemC
Symbolic Model Checking
Generating finite state machines from abstract state machines
ISSTA '02 Proceedings of the 2002 ACM SIGSOFT international symposium on Software testing and analysis
Compiling Verilog into timed finite state machines
IVC '95 Proceedings of the 4th IEEE International Verilog HDL Conference
Model-driven validation of SystemC designs
Proceedings of the 44th annual Design Automation Conference
Model checking SystemC designs using timed automata
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Model-driven validation of SystemC designs
EURASIP Journal on Embedded Systems - C-Based Design of Heterogeneous Embedded Systems
Combining Model Checking and Testing in a Continuous HW/SW Co-verification Process
TAP '09 Proceedings of the 3rd International Conference on Tests and Proofs
Scenarios for validating systemC descriptions
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Compositional semantics of system-level designs written in systemC
FSEN'07 Proceedings of the 2007 international conference on Fundamentals of software engineering
SystemC waiting state automata
International Journal of Critical Computer-Based Systems
SystemC waiting-state automata
VECoS'07 Proceedings of the First international conference on Verification and Evaluation of Computer and Communication Systems
Verifying systemC with scenario
VECoS'08 Proceedings of the Second international conference on Verification and Evaluation of Computer and Communication Systems
A HW/SW co-verification framework for SystemC
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
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SystemC is a system level language proposed to raise the abstraction level for embedded systems design and verification. In this paper, we propose to generate Finite State Machines (FSM) from SystemC designs using two algorithms originally proposed for the generation of FSM from Abstract State Machines (ASM). This proposal enables the integration of SystemC with existing tools for test case generation from FSM. Hence, enabling two important applications: (1) using the FSM graph structure to produce test suites allowing functional testing of SystemC designs; and (2) performing conformance testing, where the FSM serves as a precise model of the observable behavior of the system used to validate lower abstraction levels of the design (e.g., Register Transfer Level (RTL)).