FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Come, Let's Play: Scenario-Based Programming Using LSC's and the Play-Engine
Come, Let's Play: Scenario-Based Programming Using LSC's and the Play-Engine
LusSy: A Toolbox for the Analysis of Systems-on-a-Chip at the Transactional Level
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
Pinapa: an extraction tool for SystemC descriptions of systems-on-a-chip
Proceedings of the 5th ACM international conference on Embedded software
Formal Communication Semantics of SystemC^FL
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
Generating finite state machines from SystemC
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Learning assumptions for compositional verification
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Symbolic compositional verification by learning assumptions
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
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This paper proposes a new approach for the analysis and verification of complex systems. The core of the method consists in combining model-checking and abstract interpretation for analysis and verification. The system is modeled by a Labeled Transition System obtained from a SystemC description, and the properties to be verified are formalized as an observer automaton with assertions. To ease the specification of properties, we introduce a dedicated language, named Scenario. The contributions of the paper are twofold: the language for describing the expected properties and behavior of a system as Scenario, and a static analysis for verifying such properties.