Pinapa: an extraction tool for SystemC descriptions of systems-on-a-chip
Proceedings of the 5th ACM international conference on Embedded software
Partial order reduction for scalable testing of systemC TLM designs
Proceedings of the 45th annual Design Automation Conference
Predictive runtime verification of multi-processor SoCs in SystemC
Proceedings of the 45th annual Design Automation Conference
A Schedulerless Semantics of TLM Models Written in SystemC Via Translation into LOTOS
FM '08 Proceedings of the 15th international symposium on Formal Methods
A temporal language for SystemC
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Scenarios for validating systemC descriptions
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Test coverage for loose timing annotations
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Reactivity in systemC transaction-level models
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
PinaVM: a systemC front-end based on an executable intermediate representation
EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
Verifying SystemC: a software model checking approach
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
KRATOS: a software model checker for SystemC
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
An analytic evaluation of SystemC encodings in Promela
Proceedings of the 18th international SPIN conference on Model checking software
SystemC waiting state automata
International Journal of Critical Computer-Based Systems
Automatic RTL Test Generation from SystemC TLM Specifications
ACM Transactions on Embedded Computing Systems (TECS)
SystemC waiting-state automata
VECoS'07 Proceedings of the First international conference on Verification and Evaluation of Computer and Communication Systems
Verifying systemC with scenario
VECoS'08 Proceedings of the Second international conference on Verification and Evaluation of Computer and Communication Systems
Formal Analysis of SystemC Designs in Process Algebra
Fundamenta Informaticae
Facilitating the design of fault tolerance in transaction level SystemC programs
Theoretical Computer Science
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We describe a toolbox for the analysis of Systems-on-achip described in SystemC at the transactional level. The tools are able to extract information from SystemC code, and to build a set of parallel automata that capture the semantics of a SystemC design, including the transaction level specific constructs. As far as we know, this provides the first executable formal semantics of SystemC. Being implemented as a traditional compiler front-end, it is able to deal with general SystemC designs. The intermediate representation is now connected to existing formal verification tools via appropriate encodings. The toolbox is open and other tools will be used in the future.