An Algorithm for Analyzing Communicating Processes
Proceedings of the 7th International Conference on Mathematical Foundations of Programming Semantics
Abstract Interpretation of the pi-Calculus
Selected papers from the 5th LOMAPS Workshop on Analysis and Verification of Multiple-Agent Languages
Automatic Determination of Communication Topologies in Mobile Systems
SAS '98 Proceedings of the 5th International Symposium on Static Analysis
Dynamic Partitioning in Analyses of Numerical Properties
SAS '99 Proceedings of the 6th International Symposium on Static Analysis
Reachability Analysis for Formal Verification of SystemC
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
LusSy: A Toolbox for the Analysis of Systems-on-a-Chip at the Transactional Level
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
Generating finite state machines from SystemC
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Formal verification of SystemC by automatic hardware/software partitioning
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
SystemC waiting-state automata
VECoS'07 Proceedings of the First international conference on Verification and Evaluation of Computer and Communication Systems
SystemC waiting state automata
International Journal of Critical Computer-Based Systems
SystemC waiting-state automata
VECoS'07 Proceedings of the First international conference on Verification and Evaluation of Computer and Communication Systems
Building SystemC waiting state automata
VECoS'11 Proceedings of the Fifth international conference on Verification and Evaluation of Computer and Communication Systems
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Delta-cycles are basic units of SystemC modeling and they are supposed to provide the guarantee of some critical properties about interactions between concurrent processes, like determinism and liveness, which is the basis for higher-level modeling and analysis. However, uncareful design may cause serious problems at the transaction level, which break the properties that we want to ensure at the level of delta-cycles. We propose a formal model based on SystemC waiting-state automata for verifying properties of SystemC models at the transaction level within a delta-cycle and show that this model conforms to the SystemC scheduler up to delta-cycles.