The application of program verification techniques to hardware verification
25 years of DAC Papers on Twenty-five years of electronic design automation
Model checking
Symbolic execution and program testing
Communications of the ACM
The simulation semantics of systemC
Proceedings of the conference on Design, automation and test in Europe
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Principles of Program Analysis
Principles of Program Analysis
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Reachability Analysis for Formal Verification of SystemC
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
SystemC: methodologies and applications
SystemC: methodologies and applications
Formal Semantics of Synchronous SystemC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Formal verification of systemc designs using a petri-net based representation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An Operational Semantics of an Event-Driven System-Level Simulator
SEW '06 Proceedings of the 30th Annual IEEE/NASA Software Engineering Workshop
Formal verification of SystemC by automatic hardware/software partitioning
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
SystemC waiting-state automata
VECoS'07 Proceedings of the First international conference on Verification and Evaluation of Computer and Communication Systems
Timed systemC waiting-state automata
VECoS'09 Proceedings of the Third international conference on Verification and Evaluation of Computer and Communication Systems
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SystemC is becoming a de facto standard for the system-level description of system-on-chip. However most formal verification techniques used for verifying hardware components targets low level design, usually netlist or RTL, but time-to-market requirements have rushed the industry towards design paradigms that offer a very high level of abstraction. In previous works, we proposed a verification methodology based on SystemC waiting-state automata, an abstract formal model for verifying properties of SystemC at the transaction level within a delta-cycle. The main drawback of thismodel is that it should be provided manually. In this paper, we propose a method to automatically build the SystemC waiting-state automata from the SystemC code. It is based on an extended symbolic execution of the SystemC design that takes care of synchronous as well as asynchronous communications and that preserves the semantics of SystemC up to a delta-cycle.