Model checking
ACM Computing Surveys (CSUR)
Scheduling for Embedded Real-Time Systems
IEEE Design & Test
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design
Proceedings of the conference on Design, automation and test in Europe
SystemC waiting state automata
International Journal of Critical Computer-Based Systems
Building SystemC waiting state automata
VECoS'11 Proceedings of the Fifth international conference on Verification and Evaluation of Computer and Communication Systems
| Hi-index | 0.00 |
System-Level Modeling using system-level languages like SystemC or SystemVerilog is gaining more and more popularity. They are supposed to provide the garantee of critical functional properties about the interaction between concurrent processes like determinism or liveness up to a basic unit, the delta-cycle. Additionnally to this functional correctness, system level models should also provide valuable information about important non-functional properties like time constraints. Since timing properties (execution times, delays, periods, etc.) are especially important in performance verification of multiprocessing real-time embedded systems [1], we propose a formal model based on SystemC waiting-state automata [2] that conforms to the SystemC scheduler up to delta-cycles (1) and that also conforms to the provided time constraints (2).