Parametric real-time reasoning
STOC '93 Proceedings of the twenty-fifth annual ACM symposium on Theory of computing
Model checking
The simulation semantics of systemC
Proceedings of the conference on Design, automation and test in Europe
Verification of embedded systems using a petri net based representation
ISSS '00 Proceedings of the 13th international symposium on System synthesis
The SLAM project: debugging system software via static analysis
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Reliable and Precise WCET Determination for a Real-Life Processor
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Reachability Analysis for Formal Verification of SystemC
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
SystemC: methodologies and applications
SystemC: methodologies and applications
LusSy: A Toolbox for the Analysis of Systems-on-a-Chip at the Transactional Level
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
Generating finite state machines from SystemC
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Formal verification of systemc designs using a petri-net based representation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Formal verification of SystemC by automatic hardware/software partitioning
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
SystemC waiting-state automata
VECoS'07 Proceedings of the First international conference on Verification and Evaluation of Computer and Communication Systems
Timed systemC waiting-state automata
VECoS'09 Proceedings of the Third international conference on Verification and Evaluation of Computer and Communication Systems
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SystemC is becoming a de facto standard for the system level description of system-on-chip. However, most formal verification techniques used for verifying hardware components use a very low level design, usually a netlist or RTL, but time-to-market requirements have rushed the industry towards design paradigms that offer a very high level of abstraction. As part of this process, we propose a verification methodology for SystemC designs based on a combination of static code analysis and SystemC simulation semantics. We propose a new formal hybrid model for verifying properties of SystemC models at the transaction level within a delta-cycle. We prove that this model is compositional since it guarantees that possible interference between the SystemC process and its environment is already taken into account. Besides, it describes both functional and non-functional aspects of SystemsC designs, it is amenable for adding more constraints about system behaviour such as time properties and counters. Finally, we infer algorithms for symbolic composition and reduction of automata to eventually model the whole system behaviour.