Communicating sequential processes
Communicating sequential processes
Communicating reactive processes
POPL '93 Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
An efficient implementation of reactivity for modeling hardware in the scenic design environment
DAC '97 Proceedings of the 34th annual Design Automation Conference
High-Level specification and automatic generation of IP interface monitors
Proceedings of the 39th annual Design Automation Conference
System Design with SystemC
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Writing, verifying, and exploiting formal specifications for hardware designs
Writing, verifying, and exploiting formal specifications for hardware designs
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
System-on-chip validation using UML and CWL
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
LusSy: A Toolbox for the Analysis of Systems-on-a-Chip at the Transactional Level
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Formal verification of SystemC by automatic hardware/software partitioning
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Design and verification of systemc transaction-level models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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SystemC is a popular language used in modeling systemonchip implementations. To support this task at a high level of abstraction, transaction-level modeling (TLM) libraries have been recently developped. While TLM libraries are useful, it is difficult to capture the reactive nature of certain transactions with the constructs currently available in the SystemC and TLM libraries. In this paper, we propose an approach to specify and verify reactive transactions in SystemC designs. Reactive transactions are different from TLM transactions in the sense that a transaction can be killed or reset. Our approach consists of: (1) a language to describe reactive transactions that can be translated to verification monitors, (2) an architectural pattern to implement reactive transactions, and (3) the verification support to verify that the design does not deadlock, allows only legal behaviors and is always responsive. We illustrate our approach through an example of a transactional memory system where a transaction can be killed or reset before its completion. We identify the architectural patterns for reactive transactions. Our results demonstrate the feasibility of our approach as well as support for a comprehensive verification using RuleBase/NuSMV tools.