Evolving algebras 1993: Lipari guide
Specification and validation methods
Annotated bibliography on evolving algebras
Specification and validation methods
The semantics of the C++ programming language
Specification and validation methods
A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine
DATE '99 Proceedings of the conference on Design, automation and test in Europe
The simulation semantics of systemC
Proceedings of the conference on Design, automation and test in Europe
Formal Semantics for VHDL
System Design: A Practical Guide with Specc
System Design: A Practical Guide with Specc
SystemC
Formal hardware specification languages for protocol compliance verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System level design language extensions for timed/untimed digital-analog combined system design
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Verification of SpecC using predicate abstraction
Formal Methods in System Design
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We present a rigorous but transparent semantics definition of the SpecC language that covers the execution of SpecC behaviors and their interaction with the kernel process. The semantics include wait, waitfor, par, and try statements as they are introduced in SpecC. We present our definition in form of distributed Abstract State Machine (ASM) rules strictly following the lines of the SpecC Language Reference Manual [4]. We mainly see our formal semantics in three application areas. First, it is a concise, unambiguous description for documentation and standardization. Second, it applies as a high--level, pseudo code--oriented specification for the implementation of a SpecC simulator. Finally, it is a first step for SpecC synthesis in order to identify similar concepts with other languages like VHDL and SystemC for the definition of common patterns and language subsets.