System level design language extensions for timed/untimed digital-analog combined system design

  • Authors:

  • Yu Liu;Thanyapat Sakunkonchak;Satoshi Komatsu;Masahiro Fujita

  • Affiliations:

  • The University of Tokyo, Tokyo, Japan;The University of Tokyo, Tokyo, Japan;The University of Tokyo, Tokyo, Japan;The University of Tokyo, Tokyo, Japan

  • Venue:
  • GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
  • Year:
  • 2005

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Abstract

Recently, System Level Design Languages (SLDL) which can describe both hardware and software aspects of the design are getting attentions. Mixed-signal extensions of SLDL enable current discrete-oriented SLDL to describe and simulate not only digital systems but also Digital-Analog mixed-signal systems. The synchronization between discrete and continuous system is wildly regarded as a critical part in the extensions. In this paper, we present an event-driven synchronization approach for both timed and untimed system-level designs through which discrete and continuous time systems are synchronized via Analog-Digital(AD) events and Digital-Analog(DA) events. We also demonstrate how the synchronization method can be incorporated into SLDL, such as SpecC[4]'s simulation kernel. In the extended kernel, a new simulation cycle, AD time cycle is introduced. A preliminary evaluation on a spike-based current mode ADC[8] with CNT-based continuous description shows that the extended kernel works well under the timed/untimed system-level description.