Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
The cache coherence problem in shared-memory multiprocessors
The cache coherence problem in shared-memory multiprocessors
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
ACM Transactions on Programming Languages and Systems (TOPLAS)
ACM Transactions on Programming Languages and Systems (TOPLAS)
Verification of FLASH cache coherence protocol by aggregation of distributed transactions
Proceedings of the eighth annual ACM symposium on Parallel algorithms and architectures
Lamport clocks: verifying a directory cache-coherence protocol
Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures
Commit-reconcile & fences (CRF): a new memory model for architects and compiler writers
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
CACHET: an adaptive cache coherence protocol for distributed shared-memory systems
ICS '99 Proceedings of the 13th international conference on Supercomputing
Model checking
The Theory and Practice of Concurrency
The Theory and Practice of Concurrency
A New Approach for the Verification of Cache Coherence Protocols
IEEE Transactions on Parallel and Distributed Systems
Formal Verification of Delayed Consistency Protocols
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study
Euro-Par '95 Proceedings of the First International Euro-Par Conference on Parallel Processing
Automatic verification of the SCI cache coherence protocol
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Cache Coherence Verification with TLA+
FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume II
Verifying Sequential Consistency on Shared-Memory Multiprocessor Systems
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Protocol Verification by Aggregation of Distributed Transactions
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Better Verification Through Symmetry
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Using Lamport Clocks to Reason About Relaxed Memory Models
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Design and verification of adaptive cache coherence protocols
Design and verification of adaptive cache coherence protocols
Using Timestamping and History Variables to Verify Sequential Consistency
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Getting Formal Verification into Design Flow
FM '08 Proceedings of the 15th international symposium on Formal Methods
A monadic approach to automated reasoning for Bluespec SystemVerilog
Innovations in Systems and Software Engineering
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We describe two proofs of correctness for Cachet, an adaptive cache-coherence protocol. Each proof demonstrates soundness (conformance to an abstract cache memory model CRF) and liveness. One proof is manual, based on a term-rewriting system definition; the other is machine-assisted, based on a TLA formulation and using PVS. A two-stage presentation of the protocol simplifies the treatment of soundness, in the design and in the proofs, by separating all liveness concerns. The TLA formulation demands precision about what aspects of the system's behavior are observable, bringing complication to some parts which were trivial in the manual proof. Handing a completed design over for independent verification is unlikely to be successful: the prover requires detailed insight into the design, and the designer must keep correctness concerns at the forefront of the design process.