Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
Memory Access Dependencies in Shared-Memory Multiprocessors
IEEE Transactions on Software Engineering
Lockup-free caches in high-performance multiprocessors
Journal of Parallel and Distributed Computing
Performance evaluation of memory consistency models for shared-memory multiprocessors
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Delayed consistency and its effects on the miss rate of parallel programs
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
A performance study of memory consistency models
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
The detection and elimination of useless misses in multiprocessors
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
The verification of cache coherence protocols
SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
Journal of Parallel and Distributed Computing
Symbolic state model: a new approach for the verification of cache coherence protocols
Symbolic state model: a new approach for the verification of cache coherence protocols
Weak ordering—a new definition
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
The directory-based cache coherence protocol for the DASH multiprocessor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
A Unified Formalization of Four Shared-Memory Models
IEEE Transactions on Parallel and Distributed Systems
A New Approach for the Verification of Cache Coherence Protocols
IEEE Transactions on Parallel and Distributed Systems
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Better Verification Through Symmetry
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
An Integrated Methodology for the Verification of Directory-Based Cache Protocols
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
IEEE Transactions on Computers
A New Solution to Coherence Problems in Multicache Systems
IEEE Transactions on Computers
Verification techniques for cache coherence protocols
ACM Computing Surveys (CSUR)
Formal verification of complex coherence protocols using symbolic state models
Journal of the ACM (JACM)
Formal Automatic Verification of Cache Coherence in Multiprocessors with Relaxed Memory Models
IEEE Transactions on Parallel and Distributed Systems
Proofs of Correctness of Cache-Coherence Protocols
FME '01 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods for Increasing Software Productivity
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In a cache-coherent, shared-memory multiprocessor system, data consistency among cached copies can be delayed until synchronization points under relaxed memory consistency models. Some protocols called delayed consistency protocols take advantage of this flexibility to reduce cache miss rates and memory traffic. However, they are very complex and validating their correctness, even at the behavior level, is a challenge. We have successfully applied a new verification tool to verify the delayed consistency protocol at the behavior level. The method is called SSM [22] for Symbolic State Model. The contribution of this paper, besides verifying the protocol, is to demonstrate how to deal with relaxed memory models and latency tolerance hardware in the context of SSM.