Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
Memory access buffering in multiprocessors
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
The cache coherence problem in shared-memory multiprocessors
The cache coherence problem in shared-memory multiprocessors
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
Proving sequential consistency of high-performance shared memories (extended abstract)
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
Delayed consistency and its effects on the miss rate of parallel programs
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Reasoning about parallel architectures
Reasoning about parallel architectures
The verification of cache coherence protocols
SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
The Stanford FLASH multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Tempest and typhoon: user-level shared memory
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Symbolic state model: a new approach for the verification of cache coherence protocols
Symbolic state model: a new approach for the verification of cache coherence protocols
Verification techniques for cache coherence protocols
ACM Computing Surveys (CSUR)
Memory consistency and event ordering in scalable shared-memory multiprocessors
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
The directory-based cache coherence protocol for the DASH multiprocessor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Communicating sequential processes
Communications of the ACM
A New Approach for the Verification of Cache Coherence Protocols
IEEE Transactions on Parallel and Distributed Systems
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Formal Verification of Delayed Consistency Protocols
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Verifying Distributed Directory-Based Cahce Coherence Protocols: S3.mp, a Case Study
Euro-Par '95 Proceedings of the First International Euro-Par Conference on Parallel Processing
Verification of a Distributed Cache Memory by Using Abstractions
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Verifying Systems with Replicated Components in Murphi
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Better Verification Through Symmetry
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
The spotlight principle: on combining process-summarizing state abstractions
VMCAI'07 Proceedings of the 8th international conference on Verification, model checking, and abstract interpretation
High-performance fractal coherence
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
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Directory-based coherence protocols in shared-memory multiprocessors are so complex that verification techniques based on automated procedures are required to establish their correctness. State enumeration approaches are well-suited to the verification of cache protocols but they face the problem of state space explosion, leading to unacceptable verification time and memory consumption even for small system configurations. One way to manage this complexity and make the verification feasible is to map the system model to verify onto a symbolic state model (SSM). Since the number of symbolic states is considerably less than the number of system states, an exhaustive state search becomes possible, even for large-scale sytems and complex protocols.In this paper, we develop the concepts and notations to verifiy some properties of a directory-based protocol designed for non-FIFO interconnection networks. We compare the verification of the protocol with SSM and with the Stanford Mur 4 , a verification tool enumerating system states. We show that SSM is much more efficient in terms of verification time and memory consumption and therefore holds that promise of verifying much more complex protocols. A unique feature of SSM is that it verifies protocols for any system size and therefore provides reliable verification results in one run of the tool.