Behavioral consistency of C and verilog programs using bounded model checking
Proceedings of the 40th annual Design Automation Conference
Towards a C++-based design methodology facilitating sequential equivalence checking
Proceedings of the 43rd annual Design Automation Conference
Design for verification in system-level models and RTL
Proceedings of the 44th annual Design Automation Conference
A monadic approach to automated reasoning for Bluespec SystemVerilog
Innovations in Systems and Software Engineering
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It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often the case that by the end of a design project, multiple C models exist for different uses. Since a lot of time is invested in ensuring the functional correctness of these models via their use in system-level simulations, they often become "golden" functional reference models. Design teams are moving towards leveraging these system-level models to reduce the time needed for design and verification of RTL. On the design side, the use of high-level synthesis tools to synthesize RTL from C/C++ models is gaining ground for certain classes of blocks within a design. On the verification front, temporal differences at interfaces and in internal states between system-level models and RTL prevent the use of combinational equivalence checkers. This paper focuses on the use of sequential equivalence checking to verify functional equivalence between system-level models and RTL and describes the challenges and vale of using it in system-level to RTL flows.