Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Towards a C++-based design methodology facilitating sequential equivalence checking
Proceedings of the 43rd annual Design Automation Conference
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Strategies for mainstream usage of formal verification
Proceedings of the 45th annual Design Automation Conference
Challenges in using system-level models for RTL verification
Proceedings of the 45th annual Design Automation Conference
Leveraging sequential equivalence checking to enable system-level to RTL flows
Proceedings of the 45th annual Design Automation Conference
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It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often the case that by the end of a design project, multiple C models exist for different uses. Clearly, this leads to wasted effort on the part of model developers, and creates risk of functional divergence across models. In this paper we present some guidelines for system-level modeling and RTL design to allow for efficiently leveraging the system-level model for RTL verification via simulation based techniques, as well as via sequential equivalence checking. The paper presents the challenges of keeping system-level models and RTL synchronized from a functional perspective and presents some techniques for overcoming these challenges.