Action Systems in Pipelined Processor Design

Authors:
Juha Plosila;Kaisa Sere
Affiliations:
-;-
Venue:
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Year:
1997

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Abstract

We show that the action systems framework combined with the refinement calculus is a powerful method for handling a central problem in hardware design, the design of pipelines. We present a methodology for developing asynchronous pipelined microprocessors relying on this framework. Each functional unit of the processor is stepwise brought about which leads to a structured and modular design. The handling of different hazard situations is realized when verifying refinement steps. Our design is carried out with circuit implementation using speed-independent techniques in mind.