Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Logic in Computer Science: Modelling and Reasoning about Systems
Logic in Computer Science: Modelling and Reasoning about Systems
High-level synthesis: an essential ingredient for designing complex ASICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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Development of multi-million gate SoCs/ICs enabled by advances in submicron technology inherit verification complexity due to feature diversity on a single die and thus convergence of multiple design disciplines on one project with time-to-market pressures unchanged. For example, it is not uncommon for SoCs to integrate mixed-signal components, provide power-management features, contain instances of soft as well as hard 3rd party IPs or large building blocks developed in-house and support compliance/compatibility requirements ranging from functional to electrical aspects for various standard-based protocols. Timely and high-confidence verification sign-off for such SoCs/ICs requires a multi-prong strategy defined in this paper as holistic verification. Holistic verification emphasizes a cocktail of verification methodologies designed to address specific verification challenges of a given SoC as well as advocates aspects of verification planning and design-for-verification techniques that aid verification efforts and enhance verification efficiency. Additionally, this paper describes details of verification challenges associated with mixed-signal integration and power management features of SoCs -- two distinctly different design disciplines converging in one project and thus adding growing complexity to verification.