An application of functional decomposition in ROM-based FSM implementation in FPGA devices

Authors:
Mariusz Rawski;Henry Selvaraj;Tadeusz Łuba
Affiliations:
Institute of Telecommunications, Warsaw University of Technology, Nowowiejska 15119, 00-665 Warsaw, Poland;University of Nevada, Las Vegas 4505 Maryland Parkway, Las Vegas, NV;Institute of Telecommunications, Warsaw University of Technology, Nowowiejska 15119, 00-665 Warsaw, Poland
Venue:
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
Year:
2005

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Abstract

Modern FPLD devices have very complex structure. They combine PLA like structures, as well as FPGA and even memory-based structures. However lack of appropriate synthesis methods do not allow fully exploiting the possibilities the modern FPLDs offer. The paper presents a general method for the synthesis targeted to implementation of sequential circuits using embedded memory blocks. The method is based on the serial decomposition concept and relies on decomposing the memory block into two blocks: a combinational address modifier and a smaller memory block. An appropriately chosen decomposition strategy may allow reducing the required memory size at the cost of additional logic cells for address modifier implementation. This makes possible implementation of FSMs that exceed available memory by using embedded memory blocks and additional programmable logic.