Synthesis of fully testable circuits from BDDs

Authors:
R. Drechsler;Junhao Shi;G. Fey
Affiliations:
Inst. of Comput. Sci., Univ. of Bremen, Germany;-;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2006

Citing 0
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An approximation algorithm for fully testable kEP-SOP networks

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The optimization of kEP-SOPs: Computational complexity, approximability and experiments

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On the construction of small fully testable circuits with low depth

Microprocessors & Microsystems
FSM Encoding for BDD Representations

International Journal of Applied Mathematics and Computer Science

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Abstract

We present a technique to derive fully testable circuits under the stuck-at fault model (SAFM) and the path-delay fault model (PDFM). Starting from a function description as a binary decision diagram, the netlist is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under SAFM and PDFM. Experiments are given to show the advantages of the technique.