Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A new approach to the maximum-flow problem
Journal of the ACM (JACM)
Maximum independent sets on transitive graphs and their applications in testing and CAD
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ACTion: combining logic synthesis and technology mapping for MUX-based FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Algorithmic Graph Theory and Perfect Graphs (Annals of Discrete Mathematics, Vol 57)
Algorithmic Graph Theory and Perfect Graphs (Annals of Discrete Mathematics, Vol 57)
Synthesis of fully testable circuits from BDDs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The Binary Decision Diagram (BDD) is a powerful vehicle for large-scale functional specification and circuit design. In this paper, we consider the open problem of generating in polynomial time, the exact minimum set (T) of test vectors for detecting all single stuck-at faults in such a BDD-based circuit synthesized with multiplexors. It is shown that for a single-output circuit, T = 2k, where k is the minimum number of paths that cover all the arcs of the BDD graph. The value of k, and consequently the test set T, can be readily determined by running the max-flow algorithm on a network derived from the BDD, followed by a simple graph traversal. This procedure not only generates the optimal test set in polynomial time, but also obviates the need of employing an ATPG (Automatic Test Pattern Generator) and a fault simulator. For multi-output circuits, the procedure requires slight enhancement.