On finding the minimum test set of a BDD-based circuit
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
FPGA technology mapping with encoded libraries and staged priority cuts
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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The paper is concerned with the widely addressed problemof logic synthesis and technology mapping for multiplexerbased (MUX-based) Field-Programmable Gate Arrays(FPGAs). A novel approach for the synthesis of logicfunctions in terms of multiplexer based FPGAs (ACTELlike) has been presented in this paper. The logic functionsare represented by decomposed Binary Decision Diagrams(BDDs). The approach comprises two basic steps - optimizing decomposed BDDs with the help of ratio-parameterbased heuristic and then technology mapping ofthe optimized BDDs onto FPGA cells. Techniques like nodeduplication and sharing have been applied to minimize thenumber of FPGA cells and delay during technologymapping. Cell configurations have been chosen such thatthe switched capacitance and hence the power dissipation isminimized. The result, in terms of area, represented by thenumber of FPGA cells is comparable, but the performancein terms of delay and energy (power-delay product) aresuperior to the existing reported results.