Logic minimization using exclusive OR gates
Proceedings of the 38th annual Design Automation Conference
A Fast Partitioning Method for PLA-Based FPGAs
IEEE Design & Test
Logic synthesis for PAL-based CPLD-s based on two-stage decomposition
Journal of Systems and Software
The optimization of kEP-SOPs: Computational complexity, approximability and experiments
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Area and speed oriented synthesis of FSMs for PAL-based CPLDs
Microprocessors & Microsystems
| Hi-index | 0.01 |