Digital systems design with programmable logic
Digital systems design with programmable logic
Technology mapping for large complex PLDs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Three-Level Decomposition with Application to PLDs
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
ISMVL '01 Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic
Decomposition of Multi-Output Functions for CPLDs
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PLADE: a two-stage PLA decomposition
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient algorithm for constrained encoding and its applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Intelligent LED display technology with SCM and CPLD
IITA'09 Proceedings of the 3rd international conference on Intelligent information technology application
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A PAL-based (PAL - Programmable Array Logic) logic block is the core of a great majority of contemporary CPLD (Complex Programmable Logic Device) circuits. The purpose of the paper is to present a novel method of two-stage decomposition dedicated for PAL-based CPLD-s. The key point of the algorithm lies in sequential search for a decomposition providing feasibility of implementation of the free block in one PAL-based logic block containing a limited number of product terms. The proposed method is an alternative to the classical approach, based on two-level minimisation of separate single-output functions. An original method of determining the row multiplicity of the partition matrix is presented. For this purpose a new concept of graph is proposed - the Row Incompatibility and Complement Graph. An appropriate algorithm of the Row Incompatibility and Complement Graph colouring is presented. On the basis of row multiplicity evaluated for individual partitionings, the partitioning which provides minimisation of the bound block is chosen. Results of the experiments, which are also presented, prove that the proposed method leads to significant reduction of chip area in relation to the classical approach, especially for CPLD structures, that consist of PAL-based blocks containing 2^i (a power of 2) product terms. The proposed method was also compared with decomposition algorithms presented in another works. The results lead to a conclusion, that the proposed two-stage PAL decomposition is especially attractive with respect to the number of logic levels obtained.