High speed merged array multiplication
Journal of VLSI Signal Processing Systems
Power minimization of functional units partially guarded computation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A Simple High-Speed Multiplier Design
IEEE Transactions on Computers
Low power and high speed multiplier design with row bypassing and parallel architecture
Microelectronics Journal
A Signed Array Multiplier with Bypassing Logic
Journal of Signal Processing Systems
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths
Integration, the VLSI Journal
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This paper presents a low power digital multiplier design by taking advantage of a 2-dimensional bypassing method. The proposed bypassing cells constituting the multiplier skip redundant signal transitions as well as computations when the horizontally partial product or the vertical operand is zero. Hence, it is a 2-dimensional bypassing method. Thorough post-layout simulations of a 8脳8 digital multiplier using the proposed 2-dimensional bypassing method show that the power dissipation of the proposed design is reduced by more than 75% compared to prior designs. Physical measurements on silicon reveal that the proposed digital multiplier saves more than 28% even with pads' power dissipation compared to the prior works.