Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
High speed CMOS design styles
Clock-delayed domino for dynamic circuit design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wide Limited Switch Dynamic Logic Circuit Implementations
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Integration, the VLSI Journal
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In wide fan-in dynamic domino gates, the two phase evaluate-precharge operation leads to high switching activity at the dynamic and the output nodes which introduces a significant power penalty. In this paper, we propose a pulse domino technique to reduce the overall power consumption of a wide fan-in dynamic gate by having static-like switching behavior at the dynamic node, the gate input and the output terminals. Dynamic multiplexers designed and simulated in 90-nm CMOS are used to demonstrate the energy effectiveness of the proposed design style.